Job Description: • 5 or more years of experience in RTL design using Verilog and System Verilog • Experience in developing & optimizing DSP related RTL blocks and test and verification of DSP blocks • Previous exposure to physical layer of communication chips such as Wi-Fi, BLE, GNSS, or cellular is a plus • Design of state machines, data paths, arbitration, and clock domain crossing logic • Logic synthesis support, FPGA implementation, Timing constraints • Exposure to Design for Test, understanding of scan concept and writing DFT friendly RTL • Unified Power Format for simulation, synthesis, and electrical rule checking Equivalence checking is a plus • Accurate power estimation for RTL blocks • Committed to producing high-quality design • Team player and excellent interpersonal, communication and writing skills